This invention relates generally to operational amplifiers, and in particular, to a system and method for optimal biasing of a telescopic cascode operational transconductance amplifier (OTA).
Telescopic cascode operational transconductance amplifiers (OTAs) have gained wide popularity in the field of integrated circuit design. The reason for its popularity is that telescopic cascode OTAs generally have higher speed to current consumption ratios. That is, telescope cascode OTAs generally require lesser amount of current to achieve a given operational bandwidth as compared to other types of operational amplifiers. One undesirable characteristic of telescope cascode OTAs is that they typically have a relatively small input common mode voltage range, as will be explained in more detail with reference to FIG. 1.
FIG. 1 illustrates a schematic diagram of an exemplary prior art portion of a telescope cascode OTAs 100. The telescopic cascode OTA 100 consists of positive and negative input NMOS transistors M1 and M2, a tail current NMOS transistor M9, negative and positive output transistors M3 and M4, bias transistor B1 for biasing the gates of input transistors M1 and M2, and bias transistor B2 for biasing the gate of the tail current transistor M9. For this example, assume that the current density for transistors B2, M1, M2 and M9 are substantially the same. That is, these transistors have substantially the same I/(W/L), where I is the drain current, and W and L are respectively the width and length of the transistor channel. Also, assume that the current density for bias transistor B1 is six times that of transistors B2, M1, M2 and M9, i.e. I/(W/6L).
Given these conditions, the voltage provided to the gates of transistors M1 and M2 provided by bias transistor B1 is given by the following equation:                               Vg          ⁡                      (            B1            )                          =                  Vt          +                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                                      6                    ⁢                    L                                                                                                          Equation        ⁢                  xe2x80x83                ⁢        1            
where Vt is the device threshold voltage, xcexc is the mobility of the device channel, and Cox is the gate capacitance per unit area. The number 6 is a typical scaling factor for the device channel of transistor B1. Accordingly, the drain-to-source voltage (Vds) for the tail current transistor M9 is given by the following equation:                               Vds          ⁡                      (            M9            )                          =                  Vt          +                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                                      6                    ⁢                    L                                                                                -                      Vgs            ⁡                          (                              M1                ⁢                                  xe2x80x83                                ⁢                or                ⁢                                  xe2x80x83                                ⁢                M2                            )                                                          Equation        ⁢                  xe2x80x83                ⁢        2            
The gate-to-source voltage (Vgs) of transistors M1 and M2 is given by the following equation:                               Vgs          ⁡                      (                          M1              ⁢                              xe2x80x83                            ⁢              or              ⁢                              xe2x80x83                            ⁢              M2                        )                          =                  Vt          +                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                  L                                                                                        Equation        ⁢                  xe2x80x83                ⁢        3            
Combining equations 2 and 3, the drain-to-source voltage (Vds) for the tail current transistor M9 is given by the following relationship:                               Vds          (          M9          ⁢                      xe2x80x83                    )                =                              (                                          6                            -              1                        )                    ⁢                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                  L                                                                                        Equation        ⁢                  xe2x80x83                ⁢        4            
The minimum drain-to-source voltage which causes saturation of the drain current designated as Vdsat is given by the following equation:                               Vdsat          (          M9          ⁢                      xe2x80x83                    )                =                              Vgs            -            Vt                    =                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                  L                                                                                        Equation        ⁢                  xe2x80x83                ⁢        5            
Combining equations 4 and 5, the degree to which the tail current transistor M9 is in saturation is given by Vdsxe2x88x92Vdsat, which is given by the following relationship:                               Vds          -                      Vdsat            (            M9            ⁢                          xe2x80x83                        )                          =                              (                                          6                            -              2                        )                    ⁢                                                    2                ⁢                I                                            μ                ⁢                                  xe2x80x83                                ⁢                Cox                ⁢                                  W                  L                                                                                        Equation        ⁢                  xe2x80x83                ⁢        6            
Typically, Vdsxe2x88x92Vdsat is set to approximately 100 mVolts for transistor M9 at typical process parameters, room temperature and nominal bias current I.
Equation 6 demonstrates that the degree to which the current tail transistor M9 is in saturation is dependent on several process parameters such as the mobility xcexc of the device channel and the gate capacitance per unit area Cox. The mobility xcexc of the device channel also strongly depends on temperature. Thus, the degree to which the transistor M9 is in saturation (i.e. Vdsxe2x88x92Vdsat) depends not only on process variations but also on temperature variations. For instance, at relatively hot temperatures and slow process corner (typically termed in the art as xe2x80x9cslow process corner at hotxe2x80x9d), the mobility xcexc of the device channel and the gate capacitance per unit area Cox are relatively small. Whereas, at relatively cold temperature and fast process corner (typically termed in the art as xe2x80x9cfast process corner at coldxe2x80x9d), the mobility xcexc of the device channel and the gate capacitance per unit area Cox are relatively large. This process and temperature dependent saturation characteristic Vdsxe2x88x92Vdsat also applies to transistors M1 and M2. Further, if the bias current I is also adjustable so that the amplifier bandwidth can be adjusted, the Vdsxe2x88x92Vdsat variation is further aggravated.
Because the degree to which transistors M1, M2 and M9 are in saturation is dependent on process and temperature variations, the input common mode voltage range for the telescopic cascode OTA 100 is similarly affected. This presents a problem for the telescopic cascode OTA since it generally has a relatively small input common mode voltage range. If xcex94V is defined as Vdsxe2x88x92Vdsat for transistors M1, M2 and M9, then the input common mode range for the telescopic cascode OTA 100 is given by +/xe2x88x92xcex94V. For instance, if the amplifier 100 input voltages (IP, IN) drop more than xcex94V due to, for example, switch charge injection and/or clock feedthrough, the tail current transistor M9 would enter the linear region and the tail current is reduced. This has the negative effect of decreasing the operating bandwidth for the amplifier 100. On the other hand, if the amplifier 100 input voltages (IP, IN) rises more than xcex94V due to, for example, switch charge injection and/or clock feedthrough, the input transistors M1 and M2 would enter the linear region. This has the negative effects of decreasing the output impedance, the DC gain and accuracy of the amplifier 100.
This problem can be solved by making xcex94V=Vdsxe2x88x92Vdsat large enough to take into account variations in the input voltages so that transistors M1, M2 and M9 do not enter the linear region under all conditions. However, making xcex94V=Vdsxe2x88x92Vdsat relatively large has negative consequences. For instance, the higher xcex94V=Vdsxe2x88x92Vdsat is made, the lower is the output voltage swing of the amplifier 100. Thus, there is a need for a system and method of keeping xcex94V=Vdsxe2x88x92Vdsat for transistors M1, M2 and M9 relatively constant to prevent the transistors from entering their linear region, and relatively low to minimize the effect on the output swing of the amplifier. Such as system and method is provided herein in accordance with the invention.
One aspect of the invention includes a system and method of biasing a telescopic cascode operational transconductance amplifier to prevent or reduce the likelihood that the inputs to the amplifier exceed the common mode voltage range for the amplifier. The system and method provides a bias control circuit for the input differential transistors and tail current transistor of the operational amplifier such that their respective Vdsxe2x88x92Vdsat is maintained substantially constant. To accomplish this, the biasing system and method uses a bandgap voltage source that typically produces a highly stable voltage that is substantially temperature and process invariant. The bandgap voltage source is used to generate bias voltages applied to the gates and drains of the input differential transistors that maintains their and the tail current transistor""s Vdsxe2x88x92Vdsat substantially constant.
There are several advantages of the system and method for biasing a telescopic cascode OTA. First, by keeping Vdsxe2x88x92Vdsat substantially constant for the tail current transistor, this transistor is prevented from operating in its linear region, which would otherwise cause a decrease in the bandwidth of the amplifier. Second, by keeping (i.e. Vdsxe2x88x92Vdsat) substantially constant for the input differential transistors, these transistors are prevented from operating in their linear region, which would otherwise cause a reduction in the output impedance and the DC gain of the amplifier. Third, Vdsxe2x88x92Vdsat for the input and tail current transistors can be maintained relatively low in order to minimize the reduction of the output swing of the amplifier.